Recreating lab integrator result in LTspice simulation

I have tried to create an integrator and get a similar response to the lab photo coming from the video.

As you can see my input is symmetric but my output goes from +7.5 till -2V, Why the output is not symmetric? What is the reason?

https://www.youtube.com/watch?v=J62AVFREwxQ&t=848s







When you integrate, the solution to the integral includes a constant "offset":

$$ \int{1\cdot dt} = t + k $$

That constant \$k\$ is equal to whatever "initial conditions" existed prior to the evaluation of the integral. In the case of your electronic integrator, \$k\$ represents initial charge on the capacitor. If the capacitor holds any charge prior to the input signal being applied, or accumulates a DC charge over time, then this will appear as offset \$k\$ in your output.

There's another issue. If your input signal is not exactly symmetrical above and below zero, or doesn't have exactly 50% duty cycle, then your integrator output will rise further than it falls during each cycle, or vice versa. This will result in an output offset that gets more pronounced with each cycle:

$$ \int{1.1\cdot dt} + \int{-0.9\cdot dt} \ne 0 $$

$$ \int^{t=0.49}_{t=0.00}{1\cdot dt} + \int^{t=1.00}_{t=0.49}{-1\cdot dt} \ne 0 $$

Looking at your yellow input waveform, I can see a huge asymmetry. The yellow 0V marker (to the right) is well above the center of the waveform. You'll need to fix that before you make any other changes. Input potential must rise the same amount above zero as it falls below zero, so that its average is exactly 0V.

There is yet another problem. A real-life op-amp is not perfect. It will have a permanent non-zero voltage offset at its inputs, which result in an error in the output. It's such a small error that we can often ignore it, but in the case of an integrator, that error is accumulated over time, and results in a slowly increasing/decreasing output offset, even when everything else is perfect, such as perfect input voltage symmetry, and exactly 50% duty cycle.

In practice we include a very large resistance, R2 below, in parallel with the capacitor, to prevent a DC accumulation:



simulate this circuit – Schematic created using CircuitLab

Just make sure that \$R_2 >> R_1\$.

The design has infinite DC gain (open loop gain in non-ideal opamp) and it will amplify whatever opamp non-ideality which can be modeled as input voltage offset. By creating a 100 DC gain and setting the initial condition of the capacitor (\$IC=0 V\$), to reduce the settling time, this is new behaviour:



Even with reduced gain, a small asymmetry (10 mV below) in the input signal will be amplified:



The way LTspice works is that it solves the circuit at t=0 before the simulation starts, as if the circuit was in that state for a very long time. That means that capacitors are considered open-circuit and inductors as shorts (or DC resistance). This is called the 'initial operating point' solution.

In this case you have a -100mV applied to the integrator so the op-amp will, of course, rail in the positive direction because you've integrated that voltage (effectively) forever. With this particular op-amp that means almost +7.5V out at the very beginning of the transient simulation.

The transient simulation starts off with the op-amp railed, meaning that after a symmetrical input it will return on the next negative half-cycle to close to being railed (or a bit worse, depending on imperfections in the behavior of the components).

If I change the simulation command to skip the initial operating point solution (.tran 300u uic) and change the pulse to PULSE(-.1 .1 25u 1n 1n 50u 100u 2), I can get a symmetrical +/-5V output in simulation. The initial 25 microsecond delay gets the output to +5V in preparation for the positive half-cycle driving it down to -5V.

In a real circuit the integrator will tend to drift towards one rail or another if it isn't there already from any slight imbalance in the input, any input offset etc., unless there's something like an outside loop or a degraded capacitor (with a parallel resistor) preventing that from happening. For only a couple of cycles you could also use additional circuitry to set the initial condition in a real circuit, but after many cycles it will likely be hitting one rail or the other.